1. Field of the Invention
The present invention relates to flash memory technology, and more particularly to flash memory suitable for high density implementations.
2. Description of Related Art
Flash memory is a class of nonvolatile integrated circuit memory technology. Traditional flash memory employs floating gate memory cells. Another type of memory cell used for flash memory can be referred to as a charge trapping memory cell, which uses a dielectric charge trapping layer in place of the floating gate.
The typical flash memory cell consists of a field effect transistor FET structure having a source and drain separated by a channel, and a gate separated from the channel by a charge storage structure including a tunnel dielectric layer, the charge storage layer (floating gate or dielectric), and a blocking dielectric layer. According to the early conventional charge trapping memory designs referred to as SONOS devices, the source, drain and channel are formed in a silicon substrate (S), the tunnel dielectric layer is formed of silicon oxide (O), the charge storage layer is formed of silicon nitride (N), the blocking dielectric layer is formed of silicon oxide (O), and the gate comprises polysilicon (S).
Data is stored in a flash memory device by controlling the amount of charge trapped in the charge storage structure. The amount of charge stored sets a threshold voltage for the memory cell in flash memory devices, which allows the data to be sensed.
As specifications for the values of target threshold voltages tighten for low voltage applications, and for applications that store multiple bits per cell, problems are arising with charge retention over many data sensing cycles. Specifically, problems arise with minimizing the effects of noise that in the cells and preventing unwanted charge tunneling into memory cells by operations directed at other cells.
For sensing operations performed on strings of memory cells, biasing techniques can be applied to limit the effects of noise that is introduced into the cells which is caused by the charging of bit lines in preparation for sensing a bit stored in a memory cell. For example, as the bit line is being charged, the strings of memory cells can be isolated from the bit line by opening the string select switches that connect such strings to the bit line.
While this technique of opening the string select switch during bit line setup can limit the effects of noise on the memory cells, it can introduce another problem of unwanted charge tunneling into cells created through self-induced capacitive boosting within the strings of memory cells. For example, if the string select switch is open, preventing current flow to the bit line from the string, when a voltage that is below the high threshold voltage level is placed on a selected memory cell that is in a high threshold voltage state, the current path throughout the entire semiconductor body of the memory cells in the string is broken at the selected cell. This leaves the section between the selected cell and the string select switch floating. The voltage transitions, of pass voltages on the memory cells with floating semiconductor bodies, cause capacitive boosting. Such boosting in turn creates an electric field causing unwanted charge to tunnel into the selected cell or other cells, through hot carrier injection for example.
It is therefore desirable to provide a new memory technology that provides reduced capacitive boosting while still limiting the amount of noise that is introduced to the cells through the charging of bit lines.